1. Field of the Invention
The present invention relates to a method for forming rugged polysilicon capacitance electrodes, that is use in dynamic random access memory processes. And more particularly, the present invention relates to a method for forming rugged polysilicon capacitance electrodes that eventually reduces process time, enhances yield, and saves production costs.
2. Description of the Prior Art
Recently, demand for dynamic random access memory (DRAM) has rapidly increased owing to widespread use of electronic equipment. In particular, it is applied relatively information industry in the computer hardware. In addition to applied information industry, large-scale integration (LSI), very large scale integration (VLSI), and ultra large-scale integration (ULSI) must use greatly dynamic random access memory. In next century, the fabricated technology of the dynamic random access memory (DRAM) is still performed a primary role. Due to electronic, information, and communication product intent to light, thin, short, and quick, which high density and large capacity of the dynamic random access memory with demand is increased.
In dynamic random access memory fabrication, high density and large capacity of the dynamic random access memory is fabricated rugged polysilicon method. This is used hemispherical surface more large surface area than plane, by using increased the capacitor of the dynamic random access memory. FIG. 1 shows stage 100 placing a semiconductor wafer into low-pressure chemical vapor deposition (LPCVD) reactor and depositing a polysilicon layer. Stage 110 shows first ion implantation in a semiconductor wafer. However, stage 120 uses 1% dilute HF, by using wet etching forming a thin chemical oxide of polysilicon surface. Moreover, stage 130 places a chip into low-pressure chemical vapor deposition (LPCVD) reactor, by using the rugged polysilicon layer to form the rugged polysilicon capacitor. Stage 140 shows second ion implantation in semiconductor wafer. Stage 150 uses wet cleaning for the second time to clean wafer. Finally, stage 160 performs an annealing process at 850.degree. C. temperature. The entire process takes about 1 to 2 days, hence not only wasting time and also resulting in yield reduction due to particle contamination on wafer surface during ion implantation and wafer cleaning outside LPCVD tube.